An increasingly important use for insulated gate field effect transistors is in low voltage and low power applications such as portable communications and portable computers, i.e., pagers, cellular phones, digital logic, memories, etc. Since low power consumption is a primary goal in these applications, these types of transistors are typically designed to operate at supply voltages of less than 3.5 volts. However, semiconductor device parameters such as threshold voltage control, body effect, subthreshold leakage currents, parasitic source/drain capacitances, source/drain to substrate breakdown voltages, and source to drain punchthrough voltages typically limit the performance of low power semiconductor devices. More particularly, the higher dopant concentration required for punchthrough protection and threshold voltage control adversely affects the body effect, parasitic source/drain capacitances, and source to drain breakdown voltages.
One technique for providing punchthrough protection and threshold voltage control includes tailoring the dopant concentration profiles of the source and drain regions such that a lateral component of the dopant concentration profiles has a sufficient dopant concentration to prevent punchthrough and control the threshold voltage. However, this technique limits the depth of the vertical component of the dopant concentration profile. A consequence of shallow vertical concentration profiles is that the source and drain regions may be consumed during silicide formation, thereby destroying these regions.
Accordingly, it would be advantageous to have a method for fabricating insulated gate field effect transistors that reduces parasitic components such as source/drain capacitances and increases source/drain to substrate breakdown voltages. In addition, the method should independently optimize a lateral source/drain to channel dopant profile and a vertical source/drain to body dopant profile. It would be of further advantage for the method to improve control of the threshold voltage by allowing shallow dopant profiles and yet prevent junction shorts during contact formation.
Further, the method should be easily integrated into insulated gate field effect transistor process flows.